In recent years, with miniaturization and increased functionality of electronic equipment, CoC-type semiconductor devices are being provided in which a plurality of semiconductor chips provided with electrodes are laminated.
As an example of such a semiconductor device, Patent Reference 1 (Laid-open Japanese Patent Application 2010-251347) discloses a method of forming a semiconductor device by laminating semiconductor chips provided with electrodes, and fixing such a laminated chip structure on a wiring substrate, connecting corresponding bump electrodes to form a laminated chip structure. In the laminated chip structure, the spaces between these semiconductor chips are packed with an under-fill material (sealing resin) that covers the spaces between the laminated semiconductor chips and the periphery of the semiconductor chips, so as to prevent disconnection of the connections between corresponding electrodes or to prevent generation of cracks in the semiconductor chips themselves due to heat stress.
Also, Patent Reference 2 (Laid-open Japanese Patent Application 2005-277059) discloses a semiconductor device constituted by laminating a plurality of semiconductor chips having coupling faces with surface bump electrodes (surface-side contact members) in recesses (back face-side connection members) sunken from the back face thereof. Due to the provision of bonding faces in the sunken recesses, when the semiconductor chip is held by the bonding tool, there is no contact between the surface of the bonding tool and the bonding face. Even if the bonding face is crushed by pressure applied by the bonding tool, it does not readily come into contact with for example adjacent wiring. In this way, short-circuiting is unlikely, since the bonding face does not easily come into contact with adjacent wiring or the like even if the bonding face is crushed.